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1 ltc3709 3709f fast 2-phase, no r sense tm , synchronous dc/dc controller with tracking/sequencing polyphase tm valley current mode controller synchronizable to an external clock with pll coincident or ratiometric tracking sense resistor optional 2% to 90% duty cycle at 200khz t on(min) < 100ns true remote sensing differential amplifier high efficiency at both light and heavy loads power good output voltage monitor 0.6v 1% reference adjustable current limit programmable soft-start and operating frequency output overvoltage protection optional short-circuit shutdown timer 32-lead (5mm 5mm) qfn package notebook computers power supply for dsp, asic, graphic processors protected by u.s. patents, including 5481178, 6476589, 6144194, 5847554, 6177678, 6304066, 6580258, 6674274, 6462525, 6593724. high efficiency dual phase 1.5v/30a step-down converter the ltc ? 3709 is a single output, dual phase, synchronous step-down switching regulator. the controller uses a constant on-time, valley current control architecture to deliver very low duty cycles without requiring a sense resistor. operating frequency is selected by an external resistor and is compensated for variations in input supply voltage. an internal phase-locked loop allows the ltc3709 to be synchronized to an external clock. a track pin is provided for tracking or sequencing the output voltage among several ltc3709 chips or an ltc3709 and other dc/dc regulators. soft-start is ac- complished using an external timing capacitor. fault protection is provided by an output overvoltage com- parator and an optional short-circuit shutdown timer. the current limit level is user programmable. a wide supply range allows voltages as high as 31v to step down to 0.6v. features descriptio u applicatio s u v in 4.5v to 28v + track tg1 boost1 sw1 bg1 bg2 pgnd1 boost2 tg2 sw2 sense1 C sense2 C pgnd2 3709 ta01a sense1 + sense2 + 5v 324k 10 ? 4.7 f 1 f 47.5k hat2168h hat2165h hat2165h pgnd1 pgnd2 0.22 f 0.22 f hat2168h 1.22 h 1.22 h 10 f 35v 3 330 f 2.5v 4 v out 1.5v 30a v in v cc drv cc i on v rng fcb pgood ltc3709 run/ss extlpf intlpf 10k 100nf i th sgnd v fb diffout v os C v os + 1 f 1 f 15k 10k 100k 0.1 f 3.32k 680pf 20k typical applicatio u load current (a) 65 efficiency (%) power loss (w) 95 100 60 55 90 75 85 80 70 0.01 1 10 100 3709 ta01b 50 3 9 10 2 1 8 5 7 6 4 0 0.1 v in = 12v efficiency power loss efficiency and power loss , ltc and lt are registered trademarks of linear technology corporation. no rsense and polyphase are trademarks of linear technology corporation. all other trademarks are the property of their respective owners.
2 ltc3709 3709f input supply voltage (v cc , drv cc ) ............ 7v to C 0.3v boosted topside driver supply voltage (boost1, boost2) .................................. 37v to C 0.3v switch voltage (sw1, 2) ............................. 31v to C 1v sense1 + , sense2 + voltages ....................... 31v to C 1v sense1 C , sense2 C voltages .................... 10v to C 0.3v i on voltage ............................................... 31v to C0.3v (boost C sw) voltages ..............................7v to C 0.3v run/ss, pgood voltages .......................... 7v to C 0.3v track voltage ............................................7v to C 0.3v v rng voltage ................................. v cc + 0.3v to C 0.3v i th voltage ............................................... 2.7v to C 0.3v v fb voltage .............................................. 2.7v to C 0.3v intlpf, extlpf voltages ........................ 2.7v to C 0.3v v os + , v os C voltages ................................... 7v to C 0.3v fcb voltage ................................................ 7v to C 0.3v operating temperature range ................ C 40 c to 85 c junction temperature (note 2) ............................ 125 c storage temperature range ................ C 65 c to 125 c absolute axi u rati gs w ww u package/order i for atio uu w order part number LTC3709EUH exposed pad is sgnd (pin 33) must be soldered to pcb t jmax = 125 c, ja = 34 c/ w 32 31 30 29 28 27 26 25 9 10 11 12 top view 33 uh package 32-lead (5mm 5mm) plastic qfn 13 14 15 16 17 18 19 20 21 22 23 24 8 7 6 5 4 3 2 1 run/ss i th v fb track sgnd sgnd v os C diffout sense1 C pgnd1 bg1 drv cc bg2 pgnd2 sense2 C v cc v rng fcb i on pgood boost1 tg1 sw1 sense1 + v os + extlpf intlpf nc boost2 tg2 sw2 sense2 + (note 1) uh part marking 3709 the denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = drv cc = 5v, unless otherwise noted. electrical characteristics symbol parameter conditions min typ max units consult ltc marketing for parts specified with wider operating temperature ranges. main control loop i q input dc supply current normal 2.4 3 ma shutdown 25 65 a i fb fb pin input current i th = 1.2v (note 3) C 35 C 60 na v fb feedback voltage i th = 1.2v (note 3) 0.594 0.600 0.606 v ? v fb(linereg) feedback voltage line regulation v in = 4v to 6.5v (note 3) 0.02 %/v ? v fb(loadreg) feedback voltage load regulation i th = 0.5v to 2v (note 3) C 0.12 C 0.2 % g m(ea) error amplifier transconductance i th = 1.2v (note 3) 1.3 1.45 1.6 ms t on on-time v in = 20v, i on = 180 a 90 116 140 ns v in = 20v, i on = 90 a 180 233 280 ns t on(min) minimum on-time v in = 20v, i on = 540 a 45 100 ns t off(min) minimum off-time v in = 20v, i on = 90 a 250 350 ns
3 ltc3709 3709f the denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = drv cc = 5v, unless otherwise noted. electrical characteristics symbol parameter conditions min typ max units v sense(max) maximum current sense threshold v rng = 1v 124 144 166 mv v rng = 0v 86 101 119 mv v rng = v cc 177 202 234 mv v sense(min) minimum current sense threshold v rng = 1v C 60 mv v rng = 0v C 40 mv v rng = v cc C80 mv ? v fb(ov) overvoltage fault threshold 8.5 10 12.5 % ? v fb(uv) undervoltage fault threshold C 8.5 C 10 C 12.5 % v run/ss(on) run pin start threshold 0.8 1.4 2 v v run/ss(le) run pin latchoff enable threshold run/ss pin rising 3 v v run/ss(lt) run pin latchoff threshold run/ss pin falling 2.3 v i run/ss(c) soft-start charge current C 0.5 C 1.2 C3 a i run/ss(d) soft-start discharge current 0.8 2 4 a uvlo undervoltage lockout measured at v cc pin 3.9 4.2 v tg r up tg driver pull-up on-resistance tg high 2 ? tg r down tg driver pull-down on-resistance tg low 1.5 ? bg r up bg driver pull-up on-resistance bg high 3 ? bg r down bg driver pull-down on-resistance bg low 1.5 ? tracking i track track pin input current i th = 1.2v, v track = 0.2v (note 3) C100 C150 na v fb(track) feedback voltage at tracking v track = 0.1v, i th = 1.2v (note 3) 90 100 110 mv v track = 0.3v, i th = 1.2v (note 3) 290 300 310 mv v track = 0.5v, i th = 1.2v (note 3) 490 500 510 mv pgood output ? v fbh pgood upper threshold v fb rising 8.5 10 12.5 % ? v fbl pgood lower threshold v fb falling C 8.5 C 10 C 12.5 % pg delay pgood delay v fb falling 100 s ? v fb(hys) pgood hysteresis v fb returning 3.5 % i pgood pgood leakage current v pgood = 7v 1 a v pgl pgood low voltage i pgood = 5ma 0.2 0.4 v phase-lock loop i intpll_source internal pll sourcing current 20 a i intpll_sink internal pll sinking current C20 a i extpll_source external pll sourcing current 20 a i extpll_sink external pll sinking current C20 a v fcb(dc) forced continuous threshold measured with a dc voltage at fcb pin 1.9 2.1 2.3 v v fcb(ac) clock input threshold measured with a ac pulse at fcb pin 1 1.5 2 v t on(pll)1 t on1 modulation range by external pll up modulation i on1 = 180 a, v extpll = 1.8v 186 233 ns down modulation i on1 = 180 a, v extpll = 0.6v 58 80 ns t on(pll)2 t on2 modulation range by internal pll up modulation i on2 = 180 a, v intpll = 1.8v 186 233 ns down modulation i on2 = 180 a, v intpll = 0.6v 58 80 ns
4 ltc3709 3709f the denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = drv cc = 5v, unless otherwise noted. electrical characteristics symbol parameter conditions min typ max units note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: t j is calculated from the ambient temperature t a and power dissipation p d as follows: LTC3709EUH: t j = t a + (p d ? 34 c/w) note 3: the ltc3709 is tested in a feedback loop that adjusts v fb to achieve a specified error amplifier output voltage (i th ). note 4: the ltc3709e is guaranteed to meet performance specifications from 0 c to 70 c. specifications over the C40 c to 85 c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 5: r ds(on) limit is guaranteed by design and/or correlation to static test. differential amplifier a v differential gain 0.995 1.000 1.005 v/v v os input offset voltage in + = in C = 1.2v, i out = 1ma, 0.5 7 mv input referred; gain = 1 cm common mode input voltage range i out = 1ma 0 5 v cmrr common mode rejection ratio 0v < in + = in C < 5v, i out = 1ma, 45 70 db input referred i cl output current 10 40 ma gbp gain bandwidth product i out = 1ma 2 mhz sr slew rate r l = 2k 5 v/ s v o(max) maximum high output voltage i out = 1ma v cc C 1.2 v cc C 0.8 v r in input resistance measured at in + pin 80 k ?
5 ltc3709 3709f typical perfor a ce characteristics uw start-up v out 1v/div i l1 10a/div i l2 10a/div 1ms/div 3709 g01 v run/ss 5v/div sw1 5v/div sw2 5v/div 2 s/div 3709 g02 sw1 5v/div sw2 1v/div 10 s/div 3709 g03 continuous current mode (ccm) discontinuous current mode (dcm) transient response (ccm) efficiency vs load current i load 3a-18a v out 50mv/div v sw1 20v/div v sw2 20v/div 20 s/div 3709 g04 transient response (dcm) i load 3a-18a v out 50mv/div v sw1 20v/div v sw2 20v/div 20 s/div 3709 g05 load (ma) 65 efficiency (%) 95 100 60 55 90 75 85 80 70 10 1000 10000 100000 3709 g06 50 100 v in = 12v v out = 1.5v f = 220khz power loss vs load current quiescent current at v cc = 5v efficiency vs v in load current (ma) 0.01 power loss (w) 0.1 1 10 10 1000 10000 100000 3709 g07 0.001 100 v in = 12v v out = 1.5v f = 220khz v in (v) 4 efficiency (%) 90 95 20 3709 g08 85 80 8 12 16 24 100 v out = 1.5v i load = 10a f = 220khz temperature ( c) C40 C20 2.0 quiescent current (ma) 2.4 3.0 0 40 60 3709 g09 2.2 2.8 2.6 20 80
6 ltc3709 3709f typical perfor a ce characteristics uw shutdown current at v cc = 5v error amplifier g m ea load regulation temperature ( c) C40 C20 15 shutdown current ( a) 25 45 40 0 40 60 3709 g10 20 35 30 20 80 temperature ( c) C40 C20 1.2 ea g m (ms) 1.3 1.6 0 40 60 3709 g11 1.5 1.4 20 80 temperature ( c) C40 C20 0 ea load regulation (%) 0.1 0.4 0 40 60 3709 g12 0.3 0.2 20 80 v fb pin input current run/ss threshold armed threshold temperature ( c) C40 C20 C50 v fb pin input current (na) C40 C20 C25 0 40 60 3709 g13 C45 C30 C35 20 80 temperature ( c) C40 C20 0.8 run/ss threshold (v) 1.2 1.8 0 40 60 3709 g14 1.0 1.6 1.4 20 80 temperature ( c) C40 C20 2.0 armed threshold (v) 2.5 4.0 0 40 60 3709 g15 3.5 3.0 20 80 uvlo threshold on-time vs i on current current sense threshold vs i th voltage temperature ( c) C40 C20 3.5 uvlo threshold (v) 3.9 4.5 0 40 60 3709 g16 3.7 4.3 4.1 20 80 i on current ( a) 10 10 on-time (ns) 100 1000 10000 100 1000 3709 g17 i th voltage (v) 0 current sense threshold (mv) 100 150 200 2.4 3709 g18 50 0 C50 C150 0.6 1.2 1.8 C100 300 250 v rng = 2v v rng = v cc v rng = 1v v rng = 0v v rng = 0.5v
7 ltc3709 3709f typical perfor a ce characteristics uw maximum current sense threshold voltage vs v rng v rng (v) 0.5 250 300 350 1.7 3709 g19 200 150 0.8 1.1 1.4 2.0 100 50 0 maximum current sense threshold voltage (mv) uu u pi fu ctio s run/ss (pin 1): run control and soft-start input. a ca- pacitor to ground at this pin sets the ramp rate of the out- put voltage (approximately 0.5s/ f) and the time delay for overcurrent latch-off (see applications information). forc- ing this pin below 1.4v shuts down the device. i th (pin 2): error amplifier compensation point. the current comparator threshold increases with this control voltage. the voltage ranges from 0v to 2.4v with 0.8v corresponding to zero sense voltage (zero current). v fb (pin 3): error amplifier feedback input. this pin connects to the error amplifier input. it can be used to attach additional compensation components if desired. track (pin 4): tie the track pin to a resistive divider connected to the output of another ltc3709 for either coincident or ratiometric output tracking (see applica- tions information). to disable this feature, tie the pin to v cc . do not float this pin . sgnd (pins 5, 6, 33): signal ground. all small-signal components such as c ss and compensation components should connect to this ground and eventually connect to pgnd at one point. the exposed pad of the qfn package must be soldered to pcb ground. v os (pin 7): the (C) input to the differential amplifer. diffout (pin 8): the output of the differential amplifier. v os + (pin 9): the (+) input to the differential amplifier. extlpf (pin 10): filter connection for the pll. this pll is used to synchronize the ltc3709 with an external clock. intlpf (pin 11): filter connection for the pll. this pll is use to phase shift the second channel to the first channel by 180 . nc (pin 12): no connect. minimum current sense threshold voltage vs v rng v rng (v) 0.5 C40 C20 0 1.7 3709 g20 C60 C80 0.8 1.1 1.4 2.0 C100 C120 C140 minimum current sense threshold voltage (mv)
8 ltc3709 3709f uu u pi fu ctio s v cc (pin 17): main input supply. decouple this pin to sgnd with an rc filter (1 ? , 0.1 f). drv cc (pin 21): driver supply. provides supply to the driver for the bottom gate. also used for charging the bootstrap capacitor. bg1, bg2 (pins 22, 20): bottom gate drive. drives the gate of the bottom n-channel mosfet between ground and drv cc . pgnd1, pgnd2 (pins 23, 19): power ground. connect this pin closely to the source of the bottom n-channel mosfet, the (C) terminal of c drvcc and the (C) terminal of c in . sense1 , sense2 (pins 24, 18): current sense com- parator input. the (C) input to the current comparator is used to accurately kelvin sense the bottom side of the sense resistor or mosfet. sense1 + , sense2 + (pins 25, 16): current sense com- parator input. the (+) input to the current comparator is normally connected to the sw node unless using a sense resistor (see applications information). sw1, sw2 (pins 26, 15): switch node. the (C) terminal of the bootstrap capacitor c b connects here. this pin swings from a schottky diode voltage drop below ground up to v in . tg1, tg2 (pins 27, 14): top gate drive. drives the top n-channel mosfet with a voltage swing equal to drv cc superimposed on the switch node voltage sw. boost1, boost2 (pins 28, 13): boosted floating driver supply. the (+) terminal of the bootstrap capacitor c b connects here. this pin swings from a diode voltage drop below drv cc up to v in + drv cc . pgood (pin 29): power good output. open-drain logic output that is pulled to ground when output voltage is not within 10% of the regulation point. the output voltage must be out of regulation for at least 100 s before the power good output is pulled to ground. i on (pin 30): on-time current input. tie a resistor from v in to this pin to set the one-shot timer current and thereby set the switching frequency. fcb (pin 31): forced continuous and external clock input. tie this pin to ground to force continuous synchro- nous operation or to v cc to enable discontinuous mode operation at light load. feeding an external clock signal into this pin will synchronize the ltc3709 to the external clock and enable forced continuous mode. v rng (pin 32): sense voltage range input. the voltage at this pin is ten times the nominal sense voltage at maximum output current and can be programmed from 0.5v to 2v. the sense voltage defaults to 70mv when this pin is tied to ground, 140mv when tied to v cc .
9 ltc3709 3709f fu ctio al diagra u u w + clock detector fcb intlpf i on v cc c vcc r on extlpf pll1 to channel 2 ost fcnt on shdn shdn to channel 2 switch logic ov pll2 ost from channel 2 tg t on = (30pf) 0.7 i ion r s 20k q C + C + C + C + C + C + i cmp i rev tg c b m1 l1 v in d b v out + c in 0.6v ref switch logic sw sense + drv cc 5v bg pgnd sense C 0.66v 0.54v disable v fb r2 sgnd boost m2 c drvcc + c out r1 pgood diffout v os + 40k 40k 40k 40k v os C ov uv run shdn 100 s blanking v rng 1.4v 0.7v i th c c r c track q4 ea 3.3 a 1 240k q1 q2 q3 0.6v v ref i thb duplicate for second channel + C run/ss 1.2 a 6v 3709 fd c ss 1.4v 1.4v + C shed
10 ltc3709 3709f operatio u (refer to functional diagram) main control loop the ltc3709 is a constant on-time, current mode step- down controller with two channels operating 180 degrees out of phase. in normal operation, each top mosfet is turned on for a fixed interval determined by its own one- shot timer ost. when the top mosfet is turned off, the bottom mosfet is turned on until the current comparator i cmp trips, restarting the one-shot timer and repeating the cycle. the trip level of the current comparator is set by the i th voltage, which is the output of error amplifier ea. inductor current is determined by sensing the voltage between the sense C and sense + pins using either the bottom mosfet on-resistance or a separate sense resis- tor. at light load, the inductor current can drop to zero and become negative. this is detected by current reversal comparator i rev , which then shuts off the bottom mosfet, resulting in discontinuous operation. both switches will remain off with the output capacitor supplying the load current until the i th voltage rises above the zero current level (0.8v) to initiate another cycle. discontinuous mode operation is disabled when the fcb pin is tied to ground, forcing continuous synchronous operation. the main control loop is shut down by pulling the run/ss pin low, turning off both top mosfet and bottom mosfet. releasing the pin allows an internal 1.2 a current source to charge an external soft-start capacitor c ss . when this voltage reaches 1.4v, the ltc3709 turns on and begins operating with a clamp on the noninverting input of the error amplifier. this input is also the reference input of the error amplifier. as the voltage on run/ss continues to rise, the voltage on the reference input also rises at the same rate, effectively controlling output voltage slew rate. operating frequency the operating frequency is determined implicitly by the top mosfet on time and the duty cycle required to maintain regulation. the one-shot timer generates an on- time that is proportional to the ideal duty cycle, thus holding the frequency approximately constant with changes in v in . the nominal frequency can be adjusted with an external resistor r on . output overvoltage protection an overvoltage comparator, ov, guards against transient overshoots (>10%) as well as other more serious condi- tions that may overvoltage the output. in this condition, the top mosfet is turned off and the bottom mosfet is turned on and held on until the condition is cleared. power good (pgood) pin overvoltage and undervoltage comparators ov and uv pull the pgood output low if the output feedback voltage exits a 10% window around the regulation point. in addition, the output feedback voltage must be out of this window for a continuous duration of at least 100 s before the pgood is pulled low. this is to prevent any glitch on the feedback voltage from creating a false power bad signal. the pgood will indicate a good power immediately when the feedback voltage is in regulation. short-circuit detection and protection after the controller has been started and been given adequate time to charge the output capacitor, the run/ss capacitor is used in a short-circuit time-out circuit. if the output voltage falls to less than 67% of its nominal output voltage, the run/ss capacitor begins discharging on the assumption that the output is in an overcurrent and/or short-circuit condition. if the condition lasts for a long enough period, as determined by the size of the run/ss capacitor, the controller will be shut down until the run/ss pin voltage is recycled. this built-in latch off can be overridden by providing a >5 a pull-up at a compli- ance of 5v to the run/ss pin. this current shortens the soft-start period but also prevents net discharge of the run/ss capacitor during an overcurrent and/or short- circuit condition.
11 ltc3709 3709f drv cc power for the top and bottom mosfet drivers and most of the internal controller circuitry is derived from the drv cc pin. the top mosfet driver is powered from a floating bootstrap capacitor c b . this capacitor is normally recharged from drv cc through an external schottky di- ode d b when the top mosfet is turned off. differential amplifier this amplifier provides true differential output voltage sensing. sensing both v out + and v out C benefits regula- tion in high current applications and/or applications hav- ing electrical interconnection losses. this sensing also isolates the physical power ground from the physical signal ground, preventing the possibility of troublesome ground loops on the pc layout and preventing voltage errors caused by board-to-board interconnects. operatio u (refer to functional diagram) dual phase operation an internal phase-lock loop (pll1) ensures that channel 2 operates exactly at the same frequency as channel 1 and is also phase shifted by 180 , enabling the ltc3709 to operate optimally as a dual phase controller. the loop filter connected to the intlpf pin provides stability to the pll. for external clock synchronization, a second pll (pll2) is incorporated into the ltc3709. pll2 will adjust the on- time of channel 1 until its frequency is the same as the external clock. when locked, the pll2 aligns the turn on of the top mosfet of channel 1 to the rising edge of the external clock. compensation for pll2 is through the extlpf pin. second channel shutdown during light loads when fcb is tied to v cc , discontinuous mode is selected. in this mode, no reverse current is allowed. the second channel is off when i th is less than 0.8v for better efficiency. when fcb is tied to ground, forced continuous mode is selected, both channels are on and reversed current is allowed.
12 ltc3709 3709f applicatio s i for atio wu uu the basic ltc3709 application circuit is shown on the first page of this data sheet. external component selec- tion is primarily determined by the maximum load cur- rent and begins with the selection of the power mosfet switches and/or sense resistor. the inductor current is determined by the r ds(on) of the synchronous mosfet while the user has the option to use a sense resistor for a more accurate current limiting. the desired amount of ripple current and operating frequency largely deter- mines the inductor value. finally, c in is selected for its ability to handle the large rms current into the converter and c out is chosen with low enough esr to meet the output voltage ripple specification. maximum sense voltage and v rng pin inductor current is determined by measuring the voltage across the r ds(on) of the synchronous mosfet or through a sense resistance that appears between the sense C and the sense + pins. the maximum sense voltage is set by the voltage applied to the v rng pin and is equal to approxi- mately v rng /7.5. the current mode control loop will not allow the inductor current valleys to exceed v rng /(7.5 ? r sense ). in practice, one should allow some margin for variations in the ltc3709 and external component values. a good guide for selecting the sense resistance for each channel is: r v i sense rng out max = 2 10 ? ? () the voltage of the v rng pin can be set using an external resistive divider from v cc between 0.5v and 2v resulting in nominal sense voltages of 50mv to 200mv. addition- ally, the v rng pin can be tied to ground or v cc , in which case the nominal sense voltage defaults to 70mv or 140mv, respectively. the maximum allowed sense volt- age is about 1.3 times this nominal value. connecting the sense + and sense pins the ltc3709 provides the user with an optional method to sense current through a sense resistor instead of using the r ds(on) of the synchronous mosfet. when using a sense resistor, it is placed between the source of the synchro- nous mosfet and ground. to measure the voltage across this resistor, connect the sense + pin to the source end of the resistor and the sense C pin to the other end of the resistor. the sense + and sense C pin connections pro- vide the kelvin connections, ensuring accurate voltage measurement across the resistor. using a sense resistor provides a well-defined current limit, but adds cost and reduces efficiency. alternatively, one can use the synchro- nous mosfet as the current sense element by simply connecting the sense + pin to the switch node sw and the sense C pin to the source of the synchronous mosfet, eliminating the sense resistor. this improves efficiency, but one must carefully choose the mosfet on-resistance as discussed in the power mosfet selection section. power mosfet selection the ltc3709 requires four external n-channel power mosfets, two for the top (main) switches and two for the bottom (synchronous) switches. important parameters for the power mosfets are the breakdown voltage v (br)dss , threshold voltage v (gs)th , on-resistance r ds(on) , reverse transfer capacitance c rss and maximum current i ds(max) . the gate drive voltage is set by the 5v drv cc supply. consequently, logic-level threshold mosfets must be used in ltc3709 applications. if the drivers voltage is expected to drop below 5v, then sub-logic level threshold mosfets should be used. when the bottom mosfets are used as the current sense elements, particular attention must be paid to their on- resistance. mosfet on-resistance is typically specified with a maximum value r ds(on)(max) at 25 c. in this case additional margin is required to accommodate the rise in mosfet on-resistance with temperature: r r ds on max sense t ()( ) = t term is a normalization factor (unity at 25 c) accounting for the significant variation in on-resistance with temperature, typically about 0.4%/ c. junction-to- case temperature is about 20 c in most applications. for a maximum junction temperature of 100 c, using a value 100 c = 1.3 is reasonable (figure 1).
13 ltc3709 3709f applicatio s i for atio wu uu figure 1. r ds(on) vs temperature junction temperature ( c) C50 t normalized on-resistance 1.0 1.5 150 3709 f01 0.5 0 0 50 100 2.0 the power dissipated by the top and bottom mosfets strongly depends upon their respective duty cycles and the load current. when the ltc3709 is operating in continuous mode, the duty cycles for the mosfets are: d v v d vv v top out in bot in out in = = C the maximum power dissipation in the mosfets per channel is: pd i r v i cf r drv v v pd i top top out max t top ds on max in out rss ds on drv cc gs th gs th bot bot out max tbot = ? ? ? ? ? ? + ? ? ? ? ? ? () + ? ? ? ? ? ? = ? ? ? ? ? ? ??? (.)? ? ? ? ? C ?? () () ()( ) ()_ () () () () 2 05 2 11 2 2 2 2 ? ? ()( ) r ds on max both top and bottom mosfets have i 2 r losses and the top mosfet includes an additional term for transition losses, which are the largest at maximum input voltages. the bottom mosfet losses are the greatest when the bottom duty cycle is near 100%, during a short circuit or at high input voltage. a much smaller and much lower input capacitance mosfet should be used for the top mosfet in applications that have an output voltage that is less than 1/3 of the input voltage. in applications where v in >> v out , the top mosfets on resistance is normally less impor- tant for overall efficiency than its input capacitance at operating frequencies above 300khz. mosfet manufac- turers have designed special purpose devices that provide reasonably low on resistance with significantly reduced input capacitance for the main switch application in switch- ing regulators. operating frequency the choice of operating frequency is a tradeoff between efficiency and component size. low frequency operation improves efficiency by reducing mosfet switching losses but requires larger inductance and/or capacitance to main- tain low output ripple voltage. the operating frequency of ltc3709 applications is deter- mined implicitly by the one-shot timer that controls the on time, t on , of the top mosfet switch. the on-time is set by the current into the i on pin according to: t i pf on ion = () 07 30 . tying a resistor from v in to the i on pin yields an on-time inversely proportional to v in . for a down converter, this results in approximately constant frequency operation as the input supply varies: f v rpf out on = () 07 30 .? pll and frequency synchronization in the ltc3709, there are two on-chip phase-lock loops (plls). one of the plls is used to achieve frequency locking and phase separation between the two channels while the second pll is for locking onto an external clock. since the ltc3709 is a constant on-time architecture, the error signal generated by the phase detector of the pll is
14 ltc3709 3709f used to vary the on-time to achieve frequency locking and 180 phase separation. the synchronization is set up in a daisy chain manner whereby channel 2s on-time will be varied with respect to channel 1. if an external clock is present, then channel 1s on-time will be varied and channel 2 will follow suit. both plls are set up with the same capture range and the fre- quency range that the ltc3709 can be externally synchro- nized to is between 2 ? f c and 0.5 ? f c , where f c is the initial frequency setting of the two channels. it is advisable to set initial frequency as close to external frequency as possible. a limitation of both plls is when the on-time is close to the minimum (100ns). in this situation, the pll will not be able to synchronize up in frequency. to ensure proper operation of the internal phase-lock loop when no external clock is applied to the fcb pin, the intlpf pin may need to be pulled down while the output voltage is ramping up. one way to do this is to connect the anode of a silicon diode to the intlpf pin and its cathode to the pgood pin and connect a pull-up resistor between the pgood pin and v cc . refer to figure 9 for an example. inductor selection given the desired input and output voltages, the inductor value and operating frequency determine the ripple current: ? = ? ? ? ? ? ? ? ? ? ? ? ? i v fl v v l out out in ? C 1 lower ripple current reduces core losses in the inductor, esr losses in the output capacitors and output voltage ripple. highest efficiency operation is obtained at low frequency with small ripple current. however, achieving this requires a large inductor. there is a tradeoff between component size, efficiency and operating frequency. a reasonable starting point is to choose a ripple current that is about 40% of i out(max) /2. note that the largest ripple current occurs at the highest v in . to guarantee that ripple current does not exceed a specified maximum, the inductance should be chosen according to: l v fi v v out l max out in max = ? ? ? ? ? ? ? ? ? ? ? ? ? ? C () () 1 once the value for l is known, the inductors must be selected (based on the rms saturation current ratings). a variety of inductors designed for high current, low voltage applications are available from manufacturers such as sumida, toko and panasonic. schottky diode selection the schottky diodes conduct during the dead time be- tween the conduction of the power mosfet switches. it is intended to prevent the body diode of the bottom mosfet from turning on and storing charge during the dead time, which causes a modest (about 1%) efficiency loss. the diode can be rated for about one-half to one-fifth of the full load current since it is on for only a fraction of the duty cycle. in order for the diode to be effective, the inductance between the diode and the bottom mosfet must be as small as possible, mandating that these components be placed adjacently. the diode can be omitted if the effi- ciency loss is tolerable. c in and c out selection in continuous mode, the current of each top n-channel mosfet is a square wave of duty cycle v out /v in . a low esr input capacitor sized for the maximum rms current must be used. the details of a close form equation can be found in application note 77. figure 2 shows the input capacitor ripple current for a 2-phase configuration with the output voltage fixed and input voltage varied. the input ripple current is normalized against the dc output current. the graph can be used in place of tedious calculations. the minimum input ripple current can be achieved when the input voltage is twice the output voltage. applicatio s i for atio wu uu
15 ltc3709 3709f in the figure 2 graph, the local maximum input rms capacitor currents are reached when: v v k out in == 21 4 C where k 1, 2 these worst-case conditions are commonly used for design because even significant deviations do not offer much relief. note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to derate the capacitor. several capacitors may also be paralleled to meet size or height requirements in the design. always consult the capacitor manufacturer if there is any question. it is important to note that the efficiency loss is propor- tional to the input rms current squared and therefore a 2-stage implementation results in 75% less power loss when compared to a single phase design. battery/input protection fuse resistance (if used), pc board trace and connector resistance losses are also reduced by the re- duction of the input ripple current in a 2-phase system. the required amount of input capacitance is further reduced by the factor 2 due to the effective increase in the frequency of the current pulses. the selection of c out is primarily determined by the esr required to minimize voltage ripple and load step transients. the output ripple ? v out is approximately bounded by: ?? v i esr fc out l out + ? ? ? ? ? ? 1 8 since ? i l increases with input voltage, the output ripple is highest at maximum input voltage. typically, once the esr requirement is satisfied, the capacitance is adequate for filtering and has the necessary rms current rating. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. special polymer capacitors offer very low esr but have lower capacitance density than other types. tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. aluminum electrolytic capacitors have significantly higher esr, but can be used in cost-sensitive applications providing that consideration is given to ripple current ratings and long- term reliability. ceramic capacitors have excellent low esr characteristics but can have a high voltage coefficient and audible piezoelectric effects. high performance through-hole capacitors may also be used, but an addi- tional ceramic capacitor in parallel is recommended to reduce the effect of their lead inductance. top mosfet driver supply (c b , d b ) an external bootstrap capacitor c b connected to the boost pin supplies the gate drive voltage for the topside mosfet. this capacitor is charged through diode d b from drv cc when the switch node is low. note that the average voltage across c b is approximately drv cc . when the top mosfet turns on, the switch node rises to v in and the boost pin rises to approximately v in + drv cc . the boost capacitor applicatio s i for atio wu uu figure 2. rms input current comparison duty factor (v out /v in ) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0.6 0.5 0.4 0.3 0.2 0.1 0 3709 f02 rms input ripple currnet dc load current 2-phase 1-phase
16 ltc3709 3709f needs to store about 100 times the gate charge required by the top mosfet. in most applications 0.1 f to 0.47 f is adequate. discontinuous mode operation and fcb pin the fcb pin determines whether the bottom mosfet remains on when current reverses in the inductor. tying this pin to v cc enables discontinuous operation where the bottom mosfet turns off when inductor current reverses. the load current at which inductor current reverses and discontinuous operation begins depends on the amplitude of the inductor ripple current. the ripple current depends on the choice of inductor value and operating frequency as well as the input and output voltages. tying the fcb pin to ground forces continuous synchro- nous operation, allowing current to reverse at light loads and maintaining high frequency operation. besides providing a logic input to force continuous opera- tion, the fcb pin acts as the input for external clock syn- chronization. upon detecting a ttl level clock and the fre- quency is higher than the minimum allowable, channel 1 will lock on to this external clock. this will be followed by channel 2 (see pll and frequency synchronization). the ltc3709 will be forced to operate in forced continuous mode in this situation. fault conditions: current limit the maximum inductor current is inherently limited in a current mode controller by the maximum sense voltage. in the ltc3709, the maximum sense voltage is controlled by the voltage on the v rng pin. with valley current control, the maximum sense voltage and the sense resistance determine the maximum allowed inductor valley current. the corresponding output current limit is: i v r i limit sns max ds on t l =+ ? ? ? ? ? ? ? () () ? ?? 1 2 2 the current limit value should be checked to ensure that i limit(min) > i out(max) . the minimum value of current limit generally occurs with the largest v in at the highest ambi- ent temperature, conditions which cause the largest power loss in the converter. note that it is important to check for self-consistency between the assumed junction tempera- ture and the resulting value of i limit , which heats the junction. caution should be used when setting the current limit based upon the r ds(on) of the mosfets. the maximum current limit is determined by the minimum mosfet on-resistance. data sheets typically specify nominal and maximum values for r ds(on) , but not a minimum. a reasonable assumption is that the minimum r ds(on) lies the same amount below the typical value as the maximum lies above it. consult the mosfet manufacturer for further guidelines. for a more accurate current limiting, a sense resistor can be used. sense resistors in the 1w power range are easily available with 5%, 2% or 1% tolerance. the temperature coefficient of these resistors are very low, ranging from 250ppm/ c to 75ppm/ c. in this case, the denomina- tor in the above equation can simply be replaced by the r sense value. minimum off-time and dropout operation the minimum off-time t off(min) is the smallest amount of time that the ltc3709 is capable of turning on the bottom mosfet, tripping the current comparator and turning the mosfet back off. this time is generally about 250ns. the minimum off-time limit imposes a maximum duty cycle of t on /(t on + t off(min) ). if the maximum duty cycle is reached, due to a dropping input voltage for example, then the output will drop out of regulation in order to maintain the duty cycle at its limit. the minimum input voltage to avoid dropout is: vv tf in min out off min () () C? = 1 1 a plot of maximum duty cycle vs frequency is shown in figure 3. applicatio s i for atio wu uu
17 ltc3709 3709f soft-start and latchoff with the run/ss pin the run/ss pin provides a means to shut down the ltc3709 as well as a timer for soft-start and overcurrent latchoff. pulling the run/ss pin below 1.4v puts the ltc3709 into a low quiescent current shutdown (i q < 30 a). releasing the pin allows an internal 1.2 a internal current source to charge the external capacitor c ss . if run/ss has been pulled all the way to ground, there is a delay before starting of about: t v a csfc delay ss ss = = () 14 12 12 . . ?./ when the run/ss voltage reaches the on threshold (typically 1.4v), the ltc3709 begins operating with a clamp on eas reference voltage. the clamp level is one on threshold voltage below run/ss. as the voltage on run/ss continues to rise, eas reference is raised at the same rate, achieving monotonic output voltage soft-start (figure 4). when run/ss rises 0.6v above the on threshold, the reference clamp is invalidated and the internal precision reference takes over. after the controller has been started and given adequate time to charge the output capacitor, c ss is used as a short- circuit timer. after the run/ss pin charges above 3v, and if the output voltage falls below 67% of its regulated value, then a short-circuit fault is assumed. a 2 a current then begins discharging c ss . if the fault condition persists until the run/ss pin drops to 2.5v, then the controller turns off both power mosfets, shutting down the converter per- manently. the run/ss pin must be actively pulled down to ground in order to restart operation. the overcurrent protection timer requires that the soft- start timing capacitor c ss be made large enough to guar- antee that the output is in regulation by the time c ss has reached the 3v threshold. in general, this will depend upon the size of the output capacitance, output voltage and load current characteristic. a minimum soft-start capacitor can be estimated from: c ss > c out v out r sense (10 C4 [f/v s ]) overcurrent latchoff operation is not always needed or desired and can prove annoying during troubleshooting. the feature can be overridden by adding a pull-up current of >5 a to the run/ss pin. the additional current pre- vents the discharge of c ss during a fault and also shortens the soft-start period. using a resistor to v in as shown in figure 5 is simple, but slightly increases shutdown cur- rent. any pull-up network must be able to pull run/ss above the 3v threshold that arms the latchoff circuit and overcome the 2 a maximum discharge current. applicatio s i for atio wu uu figure 3. maximum switching frequency vs duty cycle 2.0 1.5 1.0 0.5 0 0 0.25 0.50 0.75 3709 f03 1.0 dropout region duty cycle (v out /v in ) switching frequency (mhz) run/ss 3709 f04 v out1 time time on threshold ? v = 0.6v figure 4. monotonic soft-start waveforms
18 ltc3709 3709f output voltage tracking the feedback voltage, v fb , will follow the track pin voltage when the track pin voltage is less than the reference voltage, v ref (0.6v). when the track pin voltage is greater than v ref , the feedback voltage will servo to v ref . when selecting components for the track pin, ensure the final steady-state voltage on the track pin is greater than v ref at the end of the tracking interval. the ltc3709 allows the user to set up start-up sequenc- ing among different supplies in either coincident tracking or ratiometric tracking as shown in figure 6. to implement the coincident tracking, connect an extra resistor divider to the output of supply 1. this resistor divider is selected to be the same as the divider across supply 2s output. the track pin of supply 2 is connected to this extra resistor divider. for the ratiometric tracking, simply connect the track pin of supply 2 to the v fb pin of supply 1. figure 7 shows this implementation. note that in the coincident tracking, output voltage of supply 1 has to be set higher than output voltage of supply 2 . note that since the shutdown trip point varies from part to part, the slave parts run/ss pin will need to be con- nected to v cc . this eliminates the possibility that different ltc3709s may shut down at different times. if output sequencing is not needed, connect the track pins to v cc . do not float these pins . applicatio s i for atio wu uu figure 6. two different forms of output voltage sequencing figure 7. setup for coincident and ratiometric tracking time (6a) coincident tracking v out1 v out2 output voltage time 3709 f06 (6b) ratiometric tracking v out1 v out2 output voltage r2 r1 supply 1 r6 3709 f07 r5 r4 r3 v out1 v out2 v fb supply 2 track ltc3709 v fb r3 r4 = r5 r6 v out2 coincidently tracks v out1 r3 r4 = r1 r2 ratiometric power up between v out1 and v out2 figure 5. run/ss pin interfacing with latchoff defeated 3.3v or 5v run/ss v in v cc run/ss d1 (5a) (5b) d2* c ss r ss * c ss *optional to override overcurrent latchoff r ss * 3709 f05 2n7002
19 ltc3709 3709f applicatio s i for atio wu uu efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. although all dissipative elements in the circuit produce losses, four main sources account for most of the losses in ltc3709 circuits: 1. dc i 2 r losses. these arise from the resistances of the mosfets, inductor and pc board traces and cause the efficiency to drop at high output currents. in continuous mode the average output current flows through l, but is chopped between the top and bottom mosfets. if the two mosfets have approximately the same r ds(on) , then the resistance of one mosfet can simply be summed with the resistances of l and the board traces to obtain the dc i 2 r loss. for example, if r ds(on) = 0.01 ? and r l = 0.005 ? , the loss will range from 0.1% up to 10% as the output current varies from 1a to 10a for a 1.5v output. 2. transition loss. this loss arises from the brief amount of time the top mosfet spends in the saturated region during switch node transitions. it depends upon the input voltage, load current, driver strength and mosfet capaci- tance, among other factors. the loss is significant at input voltages above 20v and can be estimated from: transition loss v i c f r drv v v in out rss ds on drv cc gs th gs th ? + ? ? ? ? ? ? (.)? ? ? ? ? ()_ () () 05 11 2 3. gate driver supply current. the driver current supplies the gate charge q g required to switch the power mosfets. this current is typically much larger than the control circuit current. in continuous mode operation: i gatechg = f (q g(top) + q g(bot) ) 4. c in loss. the input capacitor has the difficult job of filtering the large rms input current to the regulator. it must have a very low esr to minimize the ac i 2 r loss and sufficient capacitance to prevent the rms current from causing additional upstream losses in fuses or batteries. other losses, including c out esr loss, schottky conduc- tion loss during dead time and inductor core loss generally account for less than 2% additional loss. when making any adjustments to improve efficiency, the final arbiter is the total input current for the regulator at your operating point. if you make a change and the input current decreases, then you improved the efficiency. if there is no change in input current, then there is no change in efficiency. checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to ? i load (esr), where esr is the effective series resistance of c out . ? i load also begins to charge or discharge c out generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability prob- lems. the i th pin external components shown in figure 9 will provide adequate compensation for most applica- tions. for a detailed explanation of switching control loop theory see application note 76. design example as a design example, take a supply with the following specifications: v in = 7v to 28v (15v nominal), v out = 2.5v, i out(max) = 20a, f = 250khz. first, calculate the timing resistor: r v v khz pf k on = ()( )() = 25 0 7 250 30 476 . . and choose the inductor for about 40% ripple current at the maximum v in . maximum output current for each channel is 10a: l v khz a v v h = ()()() ? ? ? ? ? ? ? = 25 250 0 4 10 1 25 28 23 . . . .
20 ltc3709 3709f selecting a standard value of 1.8 h results in a maximum ripple current of: ? = () () ? ? ? ? ? ? = i v khz h v v a l 25 250 1 8 1 25 28 51 . . C . . next, choose the synchronous mosfet switch. choosing a si4874 (r ds(on) = 0.0083 ? (nom) 0.010 ? (max), q ja = 40 c/w) yields a nominal sense voltage of: v sns(nom) = (10a)(1.3)(0.0083 ? ) = 108mv tying v rng to 1.1v will set the current sense voltage range for a nominal value of 110mv with current limit occurring at 146mv. to check if the current limit is acceptable, assume a junction temperature of about 80 c above a 70 c ambient with 150 c = 1.5: i mv aa limit () ? () + () ? ? ? ? ? ? = 146 15 0010 1 2 51 2 24 .. .? and double check the assumed t j in the mosfet: p vv v a w bot = ? ? ? ? ? ? () ? () = 28 2 5 28 24 2 15 0010 197 2 C. .. . t j = 70 c + (1.97w)(40 c/w) = 149 c because the top mosfet is on for such a short time, an si4884 r ds(on)(max) = 0.0165 ? , c rss = 100pf, ja = 40 c/w will be sufficient. checking its power dissipation at current limit with 100 c = 1.4: p v v a v a pf khz www top = ? ? ? ? ? ? () ? () + ()( )( )( )( ) =+= 25 28 24 2 1 4 0 0165 1 7 28 12 100 250 030 040 07 2 2 . .. . ... t j = 70 c + (0.7w)(40 c/w) = 98 c the junction temperatures will be significantly less at nominal current, but this analysis shows that careful attention to heat sinking will be necessary in this circuit. c in is chosen for an rms current rating of about 10a at 85 c. the output capacitors are chosen for a low esr of 0.013 ? to minimize output voltage changes due to inductor ripple current and load steps. the ripple voltage will be only: ? v out(ripple) = ? i l(max) (esr) = (5.1a) (0.013 ? ) = 66mv however, a 0a to 10a load step will cause an output change of up to: ? v out(step) = ? i load (esr) = (10a) (0.013 ? ) = 130mv an optional 22 f ceramic output capacitor is included to minimize the effect of esl in the output ripple. the complete circuit is shown in figure 9. pc board layout checklist when laying out a pc board follow one of the two sug- gested approaches. the simple pc board layout requires a dedicated ground plane layer. also, for higher currents, it is recommended to use a multilayer board to help with heat sinking power components. ? the ground plane layer should not have any traces and it should be as close as possible to the layer with power mosfets. ? place c in , c out , mosfets, d1, d2 and inductors all in one compact area. it may help to have some compo- nents on the bottom side of the board. ? use an immediate via to connect the components to ground plane including sgnd and pgnd of ltc3709. use several larger vias for power components. ? use a compact plane for switch node (sw) to keep emi down. ? use planes for v in and v out to maintain good voltage filtering and to keep power losses low. ? flood all unused areas on all layers with copper. flood- ing with copper will reduce the temperature rise of power component. you can connect the copper areas to any dc net (v in , v out , gnd or to any other dc rail in your system). when laying out a printed circuit board, without a ground plane, use the following checklist to ensure proper opera- tion of the controller. these items are also illustrated in figure 9. applicatio s i for atio wu uu
21 ltc3709 3709f applicatio s i for atio wu uu figure 8. kelvin sensing sense + sense C (8b) sensing a resistor 3709 f08 r sense sense + sense C (8a) sensing the bottom mosfet mosfet d d d d g s s s ? segregate the signal and power grounds. all small signal components should return to the sgnd pin at one point, which is then tied to a clean point in the power ground such as the C node of c in . ? minimize impedance between input ground and output ground. ? connect pgnd1 to the source of m2 or r s1 (qfn) directly. this also applies to channel 2. ? place m2 as close to the controller as possible, keeping the pgnd1, bg1 and sw1 traces short. the same for the other channel. sw2 trace should connect to the drain of m2 directly. ? connect the input capacitor(s) c in close to the power mosfets: (+) node to drain of m1, (C) node to source of m2. this capacitor carries the mosfet ac current. ? keep the high dv/dt sw, boost and tg nodes away from sensitive small-signal nodes. ? connect the drv cc decoupling capacitor c vcc closely to the drv cc and pgnd pins. ? connect the top driver boost capacitor c b closely to the boost and sw pins. ? connect the v in pin decoupling capacitor c f closely to the v cc and pgnd pins. ? are the sense C and sense + leads routed together with minimum pc trace spacing? the filter capacitor be- tween sense C and sense + (c sense ) should be as close as possible to the ic. ensure accurate current sensing with kelvin connections at the sense resistor as shown in figure 8.
22 ltc3709 3709f applicatio s i for atio wu uu figure 9. 2-phase 2.5v/20a supply at 250khz with tracking and external synch 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 run/ss i th v fb track sgnd v os C diffout v os + extlpf intlpf nc boost2 tg2 sw2 sense2 + v rng fcb i on pgood boost1 tg1 sw1 sense1 + sense1 C pgnd1 bg1 drv cc bg2 pgnd2 sense2 C v cc LTC3709EUH sgnd track 1nf 470pf 100pf 100nf c c 470pf c b2 0.22 f 100pf 100pf c ss 0.1 f mmsd4148 (optional) 100nf 475 ? r f1 31.6k r c 20k r pgood 100k r on 476k 10k 35.7k r f2 10k 3.32k 10 ? f in pgood c out 180 f 4v 4 100pf d b1 cmdsh-3 d1 b340a l1 1.8 h v out 2.5v 20a l2 1.8 h d2 b340a d b2 cmdsh-3 1 f 1 f 1 f l1, l2: panasonic etqp6fir8bfa c out : panasonic eefueog181r m1, m3: siliconix si4884dy m2, m4: siliconix si4874dy c b1 0.22 f m1 c in 10 f 35v 3 drv cc 5v v in 7v to 28v m2 m3 m4 3709 f09 10nf +
23 ltc3709 3709f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. u package descriptio uh package 32-lead plastic qfn (5mm 5mm) (reference ltc dwg # 05-08-1693) 5.00 0.10 (4 sides) note: 1. drawing proposed to be a jedec package outline m0-220 variation whhd-(x) (to be approved) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 0.23 typ (4 sides) 31 1 2 32 bottom viewexposed pad 3.45 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 (uh) qfn 0603 0.50 bsc 0.200 ref 0.00 C 0.05 0.70 0.05 3.45 0.05 (4 sides) 4.10 0.05 5.50 0.05 0.25 0.05 package outline 0.50 bsc recommended solder pad layout
24 ltc3709 3709f lt/tp 1104 1k ?printed in usa ? linear technology corporation 2004 related parts linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com typical applicatio u low output ripple, 2-phase 12v/30a supply 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 run/ss i th v fb track sgnd v os C diffout v os + extlpf intlpf nc boost2 tg2 sw2 sense2 + v rng fcb i on pgood boost1 tg1 sw1 sense1 + sense1 C pgnd1 bg1 drv cc bg2 pgnd2 sense2 C v cc ltc3709 sgnd 5v r f1 190k 3.32k 100nf 470pf c b2 0.22 f r c 20k c c 1nf 220pf c ss 0.1 f r f2 10k drv cc 5v v in 24v + 10 ? c b1 0.22 f 100pf 100pf r pgood 100k r on 2.86m 10nf 10k 21.5k d b2 cmdsh-3 m3 m1-m4: renesas hat2167 c out : os-con 16svp150m m1 m2 m4 3709 ta02 l2 4.7 h l1 4.7 h toko fda1254 d1 b340a d2 b340a c out 150 f 16v 3 c in 10 f 35v 3 v out d b1 cmdsh-3 1 f 1 f 1 f part number description comments ltc1708 fast 2-phase dual output step-down controller pll, v in up to 36v, tracking ltc1778 wide operating range, no r sense step-down controller single channel, gn16 package ltc3413 ddr, qdr memory termination regulator 3a output current, 90% efficiency ltc3708 fast, dual no r sense , 2-phase synchronous step-down controller very fast transient response; very low duty factor tracking; minimum c in , c out ltc3728 dual, 550khz, 2-phase synchronous step-down switching regulator fixed frequency, dual output ltc3729 550khz, polyphase ? , high efficiency, synchronous step-down fixed frequency, single output, up to 12-phase switching regulator operation ltc3730/ltc3731 3-phase to 12-phase synchronous step-down controllers 40a to 240a, 4.5v v in 32v, 0.6v v out 5v ltc3732 ltc3778 wide operating range, no r sense step-down controller single channel, separate v on programming polyphase is a registered trademark of linear technology corporation.

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